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| HD-LINX TM GS1515 HDTV Serial Digital Reclocker PRELIMINARY DATA SHEET FEATURES * SMPTE 292M compliant * fully automatic adjustment free reclocker for HDTV signals * 1.485Gb/s and 1.485/1.001Gb/s operation * dual 75 co-axial cable driver outputs * reclocker bypass mode * seamless input Interface to the GS1504 HD adaptive equalizer * low power * lock detect * +5V or -5V power supply operation * 44 pin MQFP APPLICATIONS SMPTE 292M Serial Digital Routers; SMPTE 292M Serial Digital Distribution Amplifiers. ORDERING INFORMATION PART NUMBER GS1515-CQM GS1515-CTM PACKAGE 44 pin MQFP 44 pin MQFP Tape TEMPERATURE 0C to 70C 0C to 70C DESCRIPTION The GS1515 HDTV Serial Digital Reclocker is designed to automatically recover the embedded clock signal and retime the data from a SMPTE 292M compliant digital video signal. An internal low pass filter removes the high frequency jitter components from the bit-serial stream. 100 differential input termination is on-chip for seamless matching to 50 transmission lines. A dual SMPTE 292M compliant output Cable Driver is also included on-chip. The GS1515 uses the GO1515 external VCO connected to the internal PLL circuitry in order to achieve ultra low noise PLL performance. Two diagnostic features are included in the GS1515 for robust system design. The Input Jitter Indicator (IJI) indicates excessive input jitter before the Serial Digital outputs are muted and the Jitter Demodulator Function (DM) helps to debug systems and locate the source of jitter. The GS1515 is packaged in a 44 pin MQFP package and requires a single 5V power supply. The GS1515 typically draws 100mA of current. GS1515 LFS LFS PLCAP PLCAP IJI LFA CHARGE PUMP GO1515 VCO VCO PHASE DETECTOR PHASE LOCK LOGIC PLL_LOCK MUTE JITTER DEMODULATOR DM DM DFT_VEE DDI 50 DDI_VTT 50 DDI PATENT PENDING BYPASS RSET INPUT BUFFER BYPASS CABLE DRIVER SDO SDO BLOCK DIAGRAM Revision Date: January 2000 GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com www.gennum.com Document No. 522 - 23 - 01 ABSOLUTE MAXIMUM RATINGS PARAMETER Supply Voltage Input Voltage Range Input ESD Voltage VALUE -0.5 VDC to +5.5V DC -0.3 < VIN < VDD + 0.3V 2000V 0C TA to 70C -40C TS to 125C 260C GS1515 Operating Temperature Range Storage Temperature Range Lead Temperature (soldering, 10 sec) DC ELECTRICAL CHARACTERISTICS VCC = +5V, TA = 0C to 70C unless otherwise specified PARAMETER Positive Supply Voltage Power Consumption (without GO1515 VCO) TA = 25C SYMBOL VCC PD CONDITIONS MIN 4.75 TYP 5.00 500 MAX 5.25 - UNITS V mW NOTES 1 1 Cable Driver Output 800mV into 75 load, RSET = 52.3, 1% Used as a buffer O/P 200mV into 75 load, RSET = 210, 1% - - 420 - mW 3 Supply Current (without GO1515 VCO) TA = 25C VCC = 5V C Cable Driver Output 800mV into 75 load, RSET = 52.3, 1% Used as a buffer O/P 200mV into 75 load, RSET = 210, 1% - 100 125 mA 1 - 84 111 mA 3 Logic Input Low Logic Input High Logic Output Low Logic Output High Serial Input, common mode Serial Input, differential Serial Outputs, tuning range VIL VIH VOL VOH VDDI-CM VSID VSOD at 400A at 150A -0.5 2.0 2.4 2.5 + VSID/2 100 0 3.5 800 0.8 VCC + 0.5 0.5 VCC - VSID/2 800 880 V V V V V mV mV 1 1 1 1 2, 4 2, 4 4 2 522 - 23 - 01 AC ELECTRICAL CHARACTERISTICS VCC = +5 V, TA = 0 C to 70 C unless otherwise specified PARAMETER Serial Input Data Rate SYMBOL CONDITIONS MIN - TYP 1.485 or 1.485/1.001 0.5 MAX - UNITS Gb/s NOTES 1 Serial Input Jitter Tolerance Worst case modulation Eg. Square wave or histogram with two peaks Onset of errors with histogram extending tails (outliers) with major (75%) transitions within 0.4UI - - UI 3, 4 GS1515 - 0.8 - UI 4 PLL Lock Time - Asynchronous tALOCK Loop Bandwidth approximately 1.41MHz at 0.2UI input jitter modulation Loop Bandwidth approximately 129kHz at 0.2UI input jitter modulation - 60 100 ms 1 - 340 560 ms 3 PLL Lock Time - Synchronous t SLOCK Loop Bandwidth approximately 1.41MHz at 0.2UI input jitter modulation Loop Bandwidth approximately 129kHz at 0.2UI input jitter modulation - 1.25 - s 3 - 12.5 - s 3 Serial Output Data Rate BR SDO - 1.485 or 1.485/1.001 800 150 - Gb/s 1, 2 Serial Output - Signal Swing Serial Output - Rise Time 20% - 80% VSDO SDOtr RSET = 52.3, 1% No Compensation for Return Loss Return Loss Compensation RCOMP = 75, 1% LCOMP = 10nH CCOMP = 1.5pF 750 - 850 230 mV ps 1 1 - 220 255 ps 4 Serial Output - Fall Time 20% - 80% SDOtf No Compensation for Return Loss Return Loss Compensation RCOMP = 75, 1% LCOMP = 10nH CCOMP = 1.5pF - 150 230 ps 1 - 220 255 ps 4 Serial Output - Intrinsic Jitter t IJ Loop Bandwidth approximately 1.41MHz at 0.2UI input jitter modulation (jitter for clean PRN23 input and SMPTE pathological) CCP1, CCP2 = 1F CCP3 = Open RCP1 = Open CCP1, CCP2 = 5.6F CCP3 =1.0F RCP1 = 50 - 42 90 ps p-p 3 Loop Bandwidth at 0.2UI input jitter modulation BWLOOP - 1.41 - MHz 4 - 129 - kHz 4 3 522 - 23 - 01 AC ELECTRICAL CHARACTERISTICS (continued) VCC = +5 V, TA = 0 C to 70 C unless otherwise specified PARAMETER Jitter Peaking SYMBOL CONDITIONS Loop Bandwidth approximately 1.41MHz at 0.2UI input jitter modulation Loop Bandwidth approximately 129kHz at 0.2UI input jitter modulation MIN - TYP 0.05 MAX - UNITS dB NOTES 4 GS1515 - 0.05 - dB 4 Phaselock Unlock Timer NOTES 1. 100% Tested at 25C 2. Guaranteed by Design 3. Correlated Value 4. Using EB1515 10nF PLCAP - 67 - s 2, 4 PIN CONNECTIONS PLL_LOCK BYPASS SDO SDO 35 LFS DM DM NC NC 44 NC LFS NC NC LFA_VEE NC NC LFA_VCC NC NC LFA 1 2 3 4 5 6 7 8 9 10 11 12 43 42 41 40 39 38 37 36 34 33 32 31 30 29 NC CD_VCC NC RSET NC CD_VEE NC PD_VEE NC NC PD_VCC GS1515 TOP VIEW NC 28 27 26 25 24 23 22 SHIELD 13 14 15 IJI 16 17 18 19 20 21 PLCAP PLCAP SHIELD SHIELD VCO VCO DDI DFT_VEE 4 522 - 23 - 01 DDI_VTT DDI PIN DESCRIPTIONS NUMBER 1, 3, 4, 6, 7, 9, 10, 24, 25, 27, 29, 31, 33, 34, 36, 38 2 5 8 11 12 SYMBOL NC TYPE DESCRIPTION No connection. These pins are not bonded to the die. LFS LFA_VEE LFA_VCC LFA DFT_VEE INPUT POWER POWER OUTPUT POWER Loop filter capacitor connection. GS1515 Most negative power supply connection - loop filter circuitry. Most positive power supply connection - loop filter circuitry. Control signal output: control voltage for the external GO1515 VCO. Most negative power supply connection - that enables the jitter demodulator functionality, this pin should be connected to ground. If left floating, the DM function is disabled resulting in a current saving of 340A. Control signal input: PLL lock detect time constant capacitor connection. 13, 14 PLCAP, PLCAP SHIELD INPUT 15, 18, 22 No connect pins separating the DDI inputs, the VCO inputs and the loop filter components to improve noise performance. Connection to be made to ground in most cases depending upon PCB performance. INPUT Control signal inputs: differential inputs for the external VCO. The GO1515 has single ended output. In this case, the VCO input is decoupled to ground. Centre tap of the two 50 on-chip termination resistors between the DDI and the DDI inputs. Differential inputs for the serial digital signals. Most positive power supply connection - phase detector circuitry. Most negative poser supply connection - phase detector circuitry. Most negative power supply connection - cable driver circuitry. Resistor used to set the serial digital output signal swing. It is connected between here and ground with a very short trace length. Most positive power supply connection - cable driver circuitry. Differential serial digital outputs from the on-chip cable driver. These outputs require 75 pull-up resistors. Diagnostic signal: if the jitter demodulator function is not used, these pins must be left floating. Status signal output: indicates the amount of excessive jitter on the incoming DDI and DDI signals. Status signal output: lock detect and carrier detect: PLL lock indicator output used to indicate when the PLL is locked. This output is TTL compatible. When the PLL_LOCK = LOW, the serial digital outputs are muted. Control signal input: operational TTL compatible input that controls whether the input DDI and DDI signal is reclocked (BYPASS = HIGH) or is passed through the device, unreclocked (BYPASS = LOW). Muting does not affect the bypassed signal. Loop filter capacitor connection. 16, 17 VCO, VCO 19 DDI_VTT DDI, DDI PD_VCC PD_VEE CD_VEE RSET CD_VCC SDO, SDO INPUT 20, 21 23 26 28 30 INPUT POWER POWER POWER INPUT 32 35, 37 POWER OUTPUT 39, 40 DM, DM OUTPUT 41 IJI OUTPUT 42 PLL_LOCK OUTPUT 43 BYPASS INPUT 44 LFS INPUT 5 522 - 23 - 01 INPUT / OUTPUT CIRCUITS PD_VCC 5k PD_VCC GS1515 20k PLCAP 20k 10k PLCAP 100A PD_VEE DDI 50 DDI_VTT 50 DDI PD_VEE Fig. 1 DDI/DDI Input Fig. 4 PLCAP/PLCAP Output PD_VCC 5k 5k 500 LFA LFA_VCC 10k 10k 40 40 31p PD_VEE VCO 5mA 100A VCO 50 LFA_VEE LFA_VEE Fig. 2 VCO/VCO Input Fig. 5 LFA Circuit PD_VCC 25k 10k DM 10k DM LFA_VCC LFS 85A 400A LFA_VEE DFT_VEE Fig. 3 DM/DM Output Fig. 6 LFS Output 6 522 - 23 - 01 LFA_VCC 10k 5k SDO SDO LFS 100A 100A 100A 100A LFA_VEE GS1515 + CD_VEE RSET Fig. 7 LFS Input Fig. 10 SDO/SDO Output PD_VCC 10k 16k PD_VCC PLL_LOCK + V=2.4V BYPASS PD_VEE All on-chip resistors have 20% tolerance at room temperature. 100A PD_VEE Fig. 8 PLL_LOCK Output Fig. 11 BYPASS Circuit PD_VCC 10k IJI 5k VCC 30k A PD_VEE Fig. 9 IJI Output H/P E4422B 1.485 GHz SIGNAL GENERATOR CLOCK TEKTRONIX gigaBERT-1400 GENERATOR SPECIALLY MODIFIED FOR HDTV SD IN EB1515 (GS1515) RECLOCKER BOARD SD OUT TEKTRONIX CSA 803A COMMUNICATIONS SIGNAL ANALYZER TRIGGER CLOCK Fig. 12 Intrinsic Jitter Measurement Set-Up 7 522 - 23 - 01 DETAILED DESCRIPTION The GS1515 is a single standard re-timer for serial digital HDTV signals at 1.485Gb/s and 1.485/1.001Gb/s. UNIQUE SLEW PHASE LOCK LOOP (S-PLL): A unique feature of the GS1515 is the innovative slew phase lock loop (S-PLL). When a step phase change is applied to the PLL, the output phase gains constant rate of change with respect to time. This behavior is termed slew. Figure 13 shows an example of input and output phase variation over time for slew and linear (conventional) PLLs. Since the slewing is a non-linear behavior, the small signal analysis cannot be done in the same way as it is done for the standard PLL. However, it is still possible to plot input jitter transfer characteristics at a constant input jitter modulation. Lastly, because most of the PLL circuitry is digital, it is very robust similar to any other digital systems which are generally more robust than their analog counterparts. Additionally signals like DM/DM which represent the internal functionality can be generated without adding additional artifacts. Thus, system debugging is also possible with these features. The complete slew PLL is made up of several blocks including the phase detector, the charge pump and an external Voltage Controlled Oscillator (VCO). For the device descriptions, reference should be made to the Functional Block Diagram on the cover page of the data sheet. INPUT BUFFER GS1515 0.2 The input buffer is a self-biased circuit. On-chip 50 termination resistors provide a seamless interface for other HD-LINXTM products such as the GS1504 Adaptive Cable Equalizer. INPUT PHASE (UI) PHASE DETECTOR OUTPUT 0.1 0.0 SLEW PLL RESPONSE 0.2 INPUT 0.1 OUTPUT 0.0 LINEAR (CONVENTIONAL) PLL RESPONSE The phase detector portion of the slew PLL used in GS1515 is a bi-level digital phase detector. It indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. When the phase detector is locked, the data transition edges are aligned to the falling edge of the clock. The input data is then sampled by the rising edge of the clock, as shown in Figure 14. In this manner, the allowed input jitter is 1UI p-p in an ideal situation. However, due to setup and hold time, the GS1515 typically achieves 0.8UI p-p input jitter tolerance without causing any errors in this block. When the signal is locked to the internal clock, the control output from the phase detector is refreshed at the transition of each rising edge of the data input. During this time, the phase of the clock drifts in one direction. PHASE ALIGNMENT EDGE IN-PHASE CLOCK RE-TIMING EDGE PHASE (UI) Fig. 13 PLL Characteristics Slew PLLs offer several advantages such as excellent noise immunity. Because of the infinite bandwidth for an infinitely small input jitter modulation (or jitter introduced by VCO), the loop corrects for that immediately thus the small signal noise of the VCO is cancelled. The GS1515 uses an extremely clean, external VCO called the GO1515 (reference should be made to the GO1515 Data Sheet). In addition, the bi-state digital phase detector provides constant loop bandwidth that is independent of the data transition density. The loop bandwidth of a conventional tristable charge pump drops with reducing data transitions. During pathological signals, the data transition density reduces from 0.5 to 0.05, but the slew PLL's performance does not change. 0.8UI INPUT DATA WITH JITTER OUTPUT DATA Fig. 14 Phase Detector Characteristics 8 522 - 23 - 01 During pathological signals, the amount of jitter that the phase detector will add can be calculated. By choosing the proper loop bandwidth, the amount of phase detector induced jitter can also be limited. Typically, for a 1.41MHz loop bandwidth at 0.2UI input jitter modulation, the phase detector induced jitter is about 0.015UIp-p. This is not very significant, even for the pathological signals. CHARGE PUMP relationship between input jitter modulation index and bandwidth when RCP1 and CCP3 are not used. See the Typical Application Circuit artwork for the location of RCP1 and CCP3 . BW JITTER FACTOR (jitter modulation x BW) 282.9kHzUI 282.9kHzUI 282.9kHzUI 282.9kHzUI INPUT JITTER MODULATION INDEX 0.05 0.10 0.20 0.50 BANDWIDTH GS1515 The charge pump in a slew PLL is different from the charge pump in a linear PLL. There are two main functions of the charge pump. One function is to hold the frequency information of the input data. This information is held by CCP1, which is connected between LFS and LFS. The other capacitor, CCP2 between LFS and LFA_GND is used to remove common mode noise. Both CCP1, CCP2 should be the same value. The second function of the charge pump is to provide a binary control voltage to the VCO depending upon the phase detector output. The output pin, LFA controls the VCO. Internally there is a 500 pull-up resistor, which is driven with a 100A current called P. Another analog current F, with 5mA maximum drive proportional to the voltage across the CCP1 is applied at the same node. The voltage at the LFA node is VLFA_VCC - 500(P+F) at any time. Because of the integrator, F changes very slowly, whereas P could change at the positive edge of the data transition as often as a clock period. In the locked position, the average voltage at the LFA (VLFA_VCC - 500(P/2+F)) is such that VCO generates frequency , equal to the data rate clock frequency. Since P is changing all the time between 0A and 100A, there will be two levels generated at the LFA output. VCO 5.657MHz 2.828MHz 1.414MHz 565.7kHz The product of the input jitter modulation (IJM) and the bandwidth (BW) is a constant. In this case, it is 282.9kHzUI. The loop bandwidth automatically reduces with increasing input jitter, which helps in cleaning up the signal as much as possible. Using a series combination of RCP1 and CCP3 in parallel to an on-chip resistor (as shown in the Typical Application Circuit) can reduce the loop bandwidth of the GS1515. The parallel combination of the resistor is directly proportional to the bandwidth factor. For example, the on-chip 500 resistor yields 282.9kHzUI. If a 50 resistor is connected in parallel, the effective resistance will be (50 || 500) 45.45. This resistance yields a bandwidth factor of [282.9 X (45.45/500)] = 25.72kHzUI. The capacitance CCP3 in series with the RCP1 should be chosen such that the RC factor is 50F. For example, RCP1=50 would require CCP3=1F. The synchronous lock time increases with reduced bandwidth. Nominal synchronous lock time is equal to [ 0.25 x 2 /Bandwidth factor]. That is, the default bandwidth factor (282.9kHzUI) would yield 1.25s. For 25.72kHzUI, the synchronous lock time is 0.3535/25.72k=13.75s. Since the CCP1, CCP2 and CCP3 are also charged, it is measured to be about 11s which is slightly less than the calculated value of 13.75s. The K of the VCO (GO1515) is specified with a minimum of 11MHz/V and maximum of 21MHz/V which is about 32% variation. The 500 x P/2 will vary about 10%. The resulting bandwidth factor would approximately vary by 45% when no RCP1 and CCP3 are used. P by itself may vary by 30% so the variability for lower bandwidths will increase by an additional 30%. The CCP1 and CCP2 capacitors should be changed with reduced bandwidths. Smaller CCP1 and CCP2 capacitors would result in jitter peaking, lower stability, less probability of locking but at the same time lowering the asynchronous 9 522 - 23 - 01 The GO1515 is an external hybrid VCO, which has a centre frequency of 1.485GHz and is also guaranteed to provide 1.485/1.001GHz within the control voltage (3.1V - 4.65V) of the GS1515 over process, power supply and temperature. The GO1515 is a very clean frequency source and because of the internal high Q resonator, it is an order of magnitude more immune to external noise as compared to on-chip VCOs. The VCO gain, K, is nominally 16MHz/V. The control voltage around the average LFA voltage will be 500 x P/2. This will produce two frequencies off from the centre by =K x 500 x P/2. LOOP BANDWIDTH OPTIMIZATION Since the feed back loop has only digital circuits, the small signal analysis does not apply to the system. The effective loop bandwidth scales with the amount of input jitter modulation index. The following table summarizes the GS1515 lock time. Therefore, there is a trade-off between asynchronous lock time and jitter peaking/stability. These capacitors should be as large as possible for the allowable lock time and should be no smaller than the allowed value. With the recommended values, jitter peaking of less than 0.1dB has been measured at the lower loop bandwidth as shown in Figure 15. At higher loop bandwidths, it is difficult to measure jitter peaking because of the limitation of the measurement unit. Bandwidths lower than 129kHz at 0.2UI modulation have not been characterized, but it is believed that the bandwidth could be further lowered. Since a lower bandwidth has less correction for noise, extra care should be taken to minimize board noise. Figures 16 and 17 show the two measured loop bandwidths at these two settings. Table 1 summarizes the two bandwidth settings. Fig. 16 Typical Jitter Transfer Curve at setting A in Table 1 Fig. 15 Typical Jitter Peaking However, because relatively larger CCP1 and CCP2 capacitors can be used, over-damping of the loop response occurs. An accurate jitter peaking measurement of 0.1dB for the GS1515 requires the modulation source to have a constant amount of jitter modulation index (within 0.1dB or 1.2%) over the frequency range beyond the loop bandwidth. It has been determined that for 282.9kHzUI, the minimum value of the CCP1 and CCP2 capacitors should be no less than 0.5F. For added margin, 1F capacitors are recommended. The 1F value gives a lock time of about 60ms in one attempt. For 25.72kHzUI, these capacitors should be no less than 5.6F. This would result in 340ms of lock time. If needed, extra margin could be built by increasing these capacitors at the expense of a longer asynchronous lock time. . TABLE 1: Loop Bandwidth Setting Options BW FACTOR 282.9kHz 25.72kHz BW at 0.2UI JITTER MODULATION INDEX 1.41MHz 129kHz Fig. 17 Typical Jitter Transfer Curve at setting B in Table 1 RCP1 CCP3 CCP1 CCP2 ASYNCHRONOUS SYNCHRONOUS A B Open 50 Open 1.0 1.0 5.6 1.0 5.6 60ms 340ms 1.25s 11.0s 10 522 - 23 - 01 PHASE LOCK The phase lock circuit is used to determine the phase locked condition. It is done by generating a quadrature clock by delaying the in-phase clock (the clock whose falling edge is aligned to the data transition) by 166ps (0.25UI at 1.5GHz) with the tolerance of 0.05UI. When the PLL is locked, the falling edge of the in-phase clock is aligned with the data edges as shown in Figure 18. The quadrature clock is in a logic high state in the vicinity of input data transitions. The quadrature clock is sampled and latched by positive edges of the data transitions. The generated signal is low pass filtered with an RC network. The R is an on-chip 20k resistor and CPL is an external capacitor (recommended value 10nF). The time constant is about 67s, or more than a video line. PHASE ALIGNMENT EDGE IN-PHASE CLOCK RE-TIMING EDGE average of the ratio of the transitions inside the quadrature clock and outside the quadrature is available at the PLCAP/ PLCAP pins. A signal, IJI, which is the buffered signal available at the PLCAP is provided so that loading does not effect the filter circuit. The signal at IJI is referenced with the power supply such that the factor VIJI /V CC is a constant over process and power supply for a given input jitter modulation. The IJI signal has 10k output impedance. Figure 19 shows the relationship of the IJI signal with respect to the sine wave modulated input jitter. GS1515 P-P SINE WAVE JITTER IN UI 0.00 0.15 0.30 0.39 0.45 IJI VOLTAGE 4.75 4.75 4.75 4.70 4.60 4.50 4.40 4.30 4.20 4.10 3.95 0.8UI INPUT DATA WITH JITTER 0.25UI QUADERATURE CLOCK 0.48 0.52 0.55 0.58 0.60 0.63 PLCAP SIGNAL 5.0 4.8 PLCAP SIGNAL IJI SIGNAL (V) 4.6 4.4 4.2 4.0 3.8 3.6 Fig. 18 PLL Circuit Principles If the signal is not locked, the data transition phase could be anywhere with respect to the internal clock or the quadrature clock. In this case, the normalized filtered sample of the quadrature clock will be 0.5. When VCO is locked to the incoming data, data will only sample the quadrature clock when it is logic high. The normalized filtered sample quadrature clock will be 1.0. We chose a threshold of 0.66 to generate the phase lock signal. Because the threshold is lower than 1, it allows jitter to be bigger than 0.5UI before the phase lock circuit reads it as "not phase locked". INPUT JITTER INDICATOR (IJI) 0.00 0.20 0.40 0.60 0.80 INPUT JITTER (UI) Fig. 19 Input Jitter Indicator (Typical at TA = 25C) LOCK LOGIC This signal indicates the amount of excessive jitter (beyond the quadrature clock window 0.5UI), which occurs beyond the quadrature clock window (see Figure 18). All the input data transitions occurring outside the quadrature clock window, will be captured and filtered by the low pass filter as mentioned in the Phase Lock section. The running time 11 Logic is used to produce the PLL_LOCK signal which is based on the LFS signal and phase lock signal. When there is not any data input, the integrator will charge and eventually saturate at either end. By sensing the saturation of the integrator, it is determined that no data is present. If either data is not present or phase lock is low, the lock signal is made low. Logic signals are used to acquire the frequency by sweeping the integrator. Injecting a current 522 - 23 - 01 into the summing node of the integrator achieves the sweep. The sweep is disabled once phase lock is asserted. The direction of the sweep is also changed once LFS saturates at either end. MUTE GS1515 The logic controls the mute block whenever the PLL_LOCK signal has a LOW logic state. Whenever the mute signal is asserted, previous state of the output is latched. BYPASS When the outputs are used to differentially drive some other device such as the GS1508, it is recommended to use 50 transmission lines with the smallest possible signal swing while allowing 10% variation at the output swing to select the right choice of the RSET resistor. To drive the GS1508, the recommended RSET resistor is 150. There is no need to compensate for the return-loss in this situation. The uncompensated waveform at the output is shown in Figure 21. The BYPASS block bypasses the re-clocked/mute path of the data whenever a logic low input is applied to the BYPASS input. In the bypass mode, the mute does not have any effect on the outputs. Also, in the bypass mode, the internal PLL still locks to a valid HDTV signal and would show PLL_LOCK. CABLE DRIVER The output of the GS1515 is a dual/complimentary current mode cable driver stage. The output swing and impedance can be varied. The following table may be used to select the RSET resistor for the desired line impedance. Linear interpolation can be used to determine the specific value of the resistor for a given output swing at the load impedance. For linear interpolation, either Figure 20 or the information in Table 2 should be used. The admittance should be found and then, by inverting the admittance, a resistor value for the RSET can be found. The output can be used as dual 0.8V 75 cable drivers. It can also be used as a differential transmission line driver. In this case, the pull-up resistor should match the impedance of the transmission line because the pull-up resistor acts as the source impedance. When it is used in this case, a higher value of RSET resistor could be used in order to reduce the swing and to save power. Other HD-LINXTM products can handle such low input swings. It should be noted that the minimum RSET resistor cannot be less than 50 for reliability reasons because of higher current density. 1.0 Fig. 21 Uncompensated Output Eye Waveform SOURCE/END TERMINATEED OUTPUT SWING (V) 0.8 Fig. 22 Compensated Output Eye Waveform 0.6 75 0.4 50 0.2 NOTE: Figures 21 and 22 show the waveforms on an oscilloscope using a 75 to 50 pad. 0.0 0.00 0.01 0.02 0.03 1/RSET () Fig. 20 Signal Swing for Various R SET Admittances 12 522 - 23 - 01 TABLE 2: RSET Values for Various Output Load Conditions ADMITTANCE (g) OF THE RSET RESISTOR (= 1/RSET RESISTOR) 0.0020 0.0067 0.0133 0.0187 0.0192 0.0200 TRANSMISSION LINE, TERMINATED AT THE END. (PULL-UP RESISTOR AT THE SOURCE = 75) 0.094V 0.296V 0.569V 0.776V 0.796V 0.826V TRANSMISSION LINE, TERMINATED AT THE END. (PULL-UP RESISTOR AT THE SOURCE = 50) 0.063V RSET RESISTOR OUTPUT CURRENT 500.0 150.0 75.0 53.6 52.3 49.9 2.506mA 7.896mA 15.161mA 20.702mA 21.216mA 22.032mA GS1515 0.197V 0.379V 0.517V 0.530V JITTER DEMODULATION (DM) The differential jitter demodulation (DM) signal is available at the DM and DM pins. This signal is the phase correction signal of the PLL loop, which is amplified and buffered. If the input jitter is modulated, the PLL tracks the jitter if it is within loop bandwidth. To track the input jitter, the VCO has to be adjusted by the phase detector via the charge pump. Thus, the signal which controls the VCO contains the information of the input jitter modulation. The jitter demodulation signal is only valid if the input jitter is less than 0.5UIp-p. The DM/DM signals have 10k output impedance, which could be low pass filtered with appropriate capacitors to eliminate high frequency noise. DFT_VEE should be connected to GND to activate DM/DM signals. The DM signals can be used as diagnostic tools. Assume there is an HDTV SDI source, which contains excessive noise during the horizontal blanking because of the transient current flowing in the power supply. In order to discover the source of the noise, one could probe around the source board with a low frequency oscilloscope (Bandwidth < 20MHz) that is triggered with an appropriately filtered DM/DM signal. The true cause of the modulation will be synchronous and will appear as a stationary signal with respect to the DM/DM signal. Figure 23 shows an example of such a situation. An HDTV SDI signal is modulated with a modulation signal causing about 0.2UI jitter in Figure 23 (Channel 1). The GS1515 receives this signal and locks to it. Figure 23 (Channel 2) shows the DM signal. Notice the wave shape of the DM signal, which is synchronous to the modulating signal. The DM/DM signal could also be used to compare the output jitter of the HDTV signal source. Fig. 23 Jitter Demodulation Signal POWER SUPPLY NOISE REDUCITON See Application Note 522-61. 13 522 - 23 - 01 TYPICAL APPLICATION CIRCUIT 1n VCC 150R LOCK 2N4400 22k VCC LCOMP 75R 75R CCOMP RCOMP LCOMP CCOMP RCOMP 44 43 42 41 40 39 38 37 36 35 34 LFS BYPASS PLL_LOCK SDO SDO DM DM IJI NC NC CCP1 1.0 TANT + 1 NC 2 LFS 3 NC 4 NC 5 LFA_V EE 6 NC 7 NC 8 LFA_V 9 NC 10 NC 11 LFA RCP1 CCP3 NC + SDO + 4.7 TANT SDO VCC GS1515 4.7 TANT LCOMP = 10nH CCOMP = 1.5pF RCOMP = 759, 1% CCP2 1.0 TANT + NC 33 CD_VCC 32 NC 31 RSET 30 NC 29 GS1515 CD_VEE 28 NC 27 PD_VEE 26 NC 25 NC 24 23 PD_V DDI_VTT CC VCC 1n 52 R3 VCC Optional See application notes for details. 1n CC VCC 1n DFT_VEE SHIELD SHIELD SHIELD PLCAP PLCAP VCO VCO DDI DDI CTRL VEE 1n VCC NC 12 13 14 15 16 17 18 19 20 21 22 SDI 10n 1n 1n SDI All resistors in ohms, all capacitors in farads, unless otherwise shown. OUT GO1515 The figure above shows the recommended application circuit for the GS1515. The external VCO is the GO1515 and is specifically designed to be used with the GS1515. Figures 24 through 28 show an example PC board layout of the GS1515 IC and the GO1515 VCO. This application board layout does not reflect every detail of the typical application circuit but is used as a general guide to the location of the critical parts. For further circuit and layout details, refer to the EB1504/15 Evaluation Board Application Note. Fig. 25 Ground Layer SDO GND BYPASS VCC GND LOCK EB1515 Rev1 1 SDI GS1515 GO1515 SDO SDI Fig. 24 Component Placement Fig. 26 Top Copper Layer 14 522 - 23 - 01 3 4 GS1515 Fig. 27 Power Layer Fig. 28 Bottom Copper Layer EXTERNAL PCB AFFECTS RETURN LOSS In the application where the GS1515 directly drives a cable, it is possible to achieve an output return loss (ORL) of about 17dB to 1.485GHz. Care should be taken with the PCB layout. It is suggested to use the EB1515 as a reference layout. The use of very small `608' surface mount components and short distances between the components will help in designing high frequency circuits. Openings in the ground plane helps reduce PCB parasitic capacitance. For best matching, a 10nH inductor in parallel with a 75 resistor and a 1.5pF capacitor matches the 75 cable impedance. The inductor and resistor cancel the parasitic capacitance while the capacitor cancels the inductive effect of the bond wire. In order to verify the performance of any layout, a return loss measurement should be done by shorting the inductor with a piece of wire, without the GS1515 installed. Unless the artwork is an exact copy of the recommended layout, every design should be verified for output return loss. Changes in the layout should be tweaked until a return loss of 25dB is attained while the GS1515 is not mounted and LCOMP is shorted. Once the device is mounted, different inductors should be used to match the parasitic capacitance of the IC. When the right inductor is used, maximum return loss between 5MHz to 800MHz is achievable. Then the shunt capacitor between of 0.5pF to 1.5pF should be tried to increase the return loss between 800MHz and 1.5GHz. The larger inductor causes slower rise/fall time. The larger shunt capacitor causes a kink in the output waveform. Thus, the waveform must be verified to meet SMPTE 292M specifications. Since there are two levels at the output, depending upon the output state (logic high or low), measurement should be done by latching the outputs in both states. Since the actual output node voltages are different when a stream of data passing as compared to the static situation created to measure return loss, an interpolation is necessary. See the GS1508 Preliminary Data Sheet for more information. Fig. 29 Compensated Output Return Loss at Logic HIGH Fig. 30 Compensated Output Return Loss at Logic LOW 15 522 - 23 - 01 OTHER LAYOUT CONSIDERATIONS The GS1515 is a robust re-timing solution. The layout should be done such that VCO (GO1515) is close to the chip minimizing LFA and VCO traces between GS1515 and GO1515. It is recommended to use the other side of the PCB board whenever possible. The short trace of LFA will reduce noise coupling to the control pin of the VCO. The VCO trace should also be short to reduce EMI radiation from a 1.5GHz clock source. Digital switching noise from CMOS chips should be avoided for best performance. This could be done by providing a moat of at least 50mil wide in all the planes (the GND, VCC and signal layers) (One should be able to see through the moat when the PCB is fabricated). The power supply to the GS1515 Island should be provided through ferrite beads to reject the power supply spikes. TABLE 3: Application Debugging PROBLEM Output Jitter > 80ps POSSIBLE REASON Wrong way of measuring jitter. In applications where an adaptive equalizer is used with the GS1515, extra care should be taken to avoid any noise coupling between these two devices. The following recommendations should be followed as layout guides lines. Please refer to the layouts of the EB1515/04 and note the following: 1. The use of power supply islands for GS1504 Adaptive Equalizer. 2. The position of ferrite beads for power supply noise filtering. 3. The ground under the transmission line for GS1504 and GS1515 interface. 4. The transmission line decoupling at the GS1515 end to the transmission line ground. 5. The isolation moat around the transmission line reference ground. GS1515 SOLUTION Follow jitter measuring procedure as shown in Fig 12. Follow jitter measuring procedure as shown in Fig 12. Shut down the digital circuit and power the board from clean voltage regulated supply. The acceptable noise in the VCC is 5mVp-p. If the problem is resolved, filter high frequency noise with ferrite beads and low frequency noise with Inductor and Capacitor. The source of jitter could also be found using diagnostic signal DM as mentioned in the section JITTER DEMODULATION. Apply logic high at the BYPASS pin. A. Configure into bypass mode and look for output jitter under infinite persistence for about 5 minutes in a sampling scope, if total jitter including random shots is more than 0.5UI, input jitter is out of specification. Debug circuit, which is driving GS1515. Probe IJI by a low frequency digital scope to capture any glitch. If glitches are not identified, remove the 10nF PLCAP between PLCAP and PLCAP. If glitches are identified, then the sum of jitter of the reclocker and the source is more than 0.5UI. Achieve reclocker jitter around 0.1UI or less and reduce the source jitter less than 0.4UI. Bad source / trigger reference signal. Power supply noise generated either by on board digital circuit or switch mode DC power supply. Bypass mode activated. Errors being generated Bad input jitter. B. 16 522 - 23 - 01 PACKAGE DIMENSIONS 13.90 0.25 10.00 0.10 14 2 0.40 MIN 0 MIN 0.3 NOM. RADIUS 7 MAX 0 MIN GS1515 13.90 0.25 10.00 0.10 14 2 0.13 MIN. RADIUS 1.95 REF 0.80 0.15 0.80 BSC 0.45 MAX 0.30 MIN 2.10 MAX 1.95 MIN 2.35 MAX 0.25 MAX 0.10 MIN 0.18 0.05 44 pin MQFP All dimensions are in millimetres. CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION PRELIMINARY DATA SHEET This product is in production. Gennum reserves the right to make changes to the product and to the documentation. REVISION NOTES: Changed VCC to VEE in input/output circuits artwork; Changed values in DC Electrical Characteristics Table; Added notes to Figures 21 and 22 and Package Dimensions; Added reference for power supply noise reduction. For latest product information visit www.gennum.com GENNUM CORPORATION MAILING ADDRESS: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 SHIPPING ADDRESS: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 GENNUM JAPAN CORPORATION C-101, Miyamae Village, 2-10-42 Miyamae, Suginami-ku Tokyo 168-0081, Japan Tel. +81 (03) 3334-7700 Fax. +81 (03) 3247-8839 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no responsibility for the use of any circuits described herein and makes no representations that they are free from patent infringement. (c) Copyright July 1999 Gennum Corporation. All rights reserved. Printed in Canada. 17 522 - 23 - 01 |
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